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| 6HSWHPEHU 3UHOLPLQDU\ ,QIRUPDWLRQ $6/9 9 . [ . i &026 )ODVK ((3520 )HDWXUHV * Organization: 512Kx8/256Kx16 * Sector architecture - One 16K; two 8K; one 32K; and seven 64K byte sectors - One 8K; two 4K; one 16K; and seven 32K word sectors - Boot code sector architecture--T (top) or B (bottom) - Erase any combination of sectors or full chip * Single 2.7-3.6V power supply for read/write operations * Sector protection * High speed 70/80/90/120 ns address access time * Automated on-chip programming algorithm - Automatically programs/verifies data at specified address * Automated on-chip erase algorithm - Automatically preprograms/erases chip or specified sectors * Hardware RE S E T pin - Resets internal state machine to read mode * Low power consumption - 200 nA typical automatic sleep mode current - 200 nA typical standby current - 10 mA typical read current * JEDEC standard software, packages and pinouts - 48-pin TSOP - 44-pin SO; availability TBD * Detection of program/erase cycle completion - DQ7 DATA polling - DQ6 toggle bit - DQ2 toggle bit - RY/BY output * Erase suspend/resume - Supports reading data from or programming data to a sector not being erased * Low VCC write lock-out below 1.5V * 10 year data retention at 150C * 100,000 write/erase cycle endurance DQ0-DQ15 /RJLF EORFN GLDJUDP RY/BY VCC VSS Sector protect/ erase voltage switches Erase voltage generator RESET WE BYTE Command register Program/erase control Input/output buffers Program voltage generator Chip enable Output enable Logic STB Data latch CE OE A-1 VCC detector Timer Address latch STB Y decoder Y gating X decoder Cell matrix A0-A17 6HOHFWLRQ JXLGH Maximum access time Maximum chip enable access time Maximum output enable access time tAA tCE tOE 29LV400-70 70 70 30 29LV400-80 80 80 30 29LV400-90 90 90 35 29LV400-120 120 120 50 Unit ns ns ns 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 1 of 26 &RS\ULJKW $OOLDQFH 6HPLFRQGXFWRU $OO ULJKWV UHVHUYHG $6/9 3LQ DVVLJQPHQWV 48-pin TSOP NC RY/BY NC A17 A7 A6 A5 A4 A3 A2 A1 OE VSS CE A0 BY/RY NC A17 A7 A6 A5 A4 A3 A2 A1 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 AS29LV400 A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET NC AS29LV400 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 44-pin SO (availability TBD) A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RESET WE A8 A9 A10 A11 A12 A13 A14 A15 A16 DQ0 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC P. 2 of 26 $6/9 )XQFWLRQDO GHVFULSWLRQ The AS29LV400 is an 4 megabit, 3.0 volt Flash memory organized as 512Kbyte of 8 bits/256Kbytes of 16 bits each. For flexible Erase and Program capability, the 4 megabits of data is divided into eleven sectors: one 16K, two 8K, one 32K, and seven 64k byte sectors; or one 8K, two 4K, one 16K, and seven 32K word sectors. The x8 data appears on DQ0-DQ7; the x16 data appears on DQ0-DQ15. The AS29LV400 is offered in JEDEC standard 48-pin TSOP and 44-pin SO. This device is designed to be programmed and erased with a single 3.0V VCC supply. The device can also be reprogrammed in standard EPROM programmers. The AS29LV400 offers access times of 70/80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To eliminate bus contention the device has separate chip enable (C E ), write enable (WE ), and output enable (O E ) controls. Word mode (x16 output) is selected by B YT E = high. Byte mode (x8 output) is selected by BY TE = low. The AS29LV400 is fully compatible with the JEDEC single power supply Flash standard. The device uses standard microprocessor write timings to send Write commands to the register. An internal state-machine uses register contents to control the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the Programming and Erase operations. Data is read in the same manner as other Flash or EPROM devices. Use the Program command sequence to invoke the on-chip programming algorithm that automatically times the program pulse widths, and verifies proper cell margin. Use the Erase command sequence to invoke the automated on-chip erase algorithm that preprograms the sector when it is not already programmed before executing the erase operation. The Erase command also times the erase pulse widths and verifies the proper cell margins. Boot sector architecture enables the system to boot from either the top (AS29LV400T) or the bottom (AS29LV400B) sector. Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both the Program and the Erase operations in all, or any combination of the eleven sectors. The device provides true background erase with Erase Suspend, which puts erase operations on hold to either read data from, or program data to, a sector that is not being erased. The Chip Erase command will automatically erase all unprotected sectors. When shipped from the factory, AS29LV400 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1. Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other sectors. The device features a single 3.0V power supply operation for Read, Write, and Erase functions. Internally generated and regulated voltages are provided for the Program and Erase operations. A low V CC detector automatically inhibits write operations during power transtitions. The RY/BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect the end of the program or to erase operations. The device automatically resets to the Read mode after the Program or Erase operations are completed. DQ2 indicates which sectors are being erased. The AS29LV400 resists accidental erasure or spurious programming signals resulting from power transitions. The Control register architecture permits alteration of memory contents only when successful completion of specific command sequences has occured. During power up, the device is set to Read mode with all Program/Erase commands disabled if VCC is less than VLKO (lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on O E , CE , or WE . To initiate Write commands, CE and WE must be a logical zero and O E a logical 1. When the device's hardware R E S E T pin is driven low, any Program/Erase operation in progress is terminated and the internal state machine is reset to Read mode. If the RE S E T pin is tied to the system reset circuitry and a system reset occurs during an automated on-chip Program/Erase algorithm, the operating data in the address locations may become corrupted and require rewriting. Resetting the device enables the system's microprocessor to read boot-up firmware from the Flash memory. The AS29LV400 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are programmed one at a time using the EPROM programming mechanism of hot electron injection. 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 3 of 26 $6/9 2SHUDWLQJ PRGHV Mode ID read MFR code ID read device code Read Standby Output disable Write Enable sector protect Sector unprotect Temporary sector unprotect Verify sector protect Verify sector unprotect Hardware Reset CE OE WE L L L H L L L L X L L X L L L X H H VID VID X L L X H H H X H L Pulse/L Pulse/L X H H X A0 L H A0 X X A0 L L X L L X A1 L L A1 X X A1 H H X H H X A6 L L A6 X X A6 L H X L H X A9 VID VID A9 X X A9 VID VID X VID VID X R E SE T H H H H H H H H VID H H L DQ Code Code DOUT High Z High Z DIN X X X Code Code High Z L = Low ( 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 4 of 26 $6/9 0RGH GHILQLWLRQV Description Selected by A9 = VID(9.5V-10.5V), C E = O E = A1 = A6 = L, enabling outputs. ID MFR code, When A0 is low (VIL) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products. device code When A0 is high (VIH), DOUT represents the device code for the AS29LV400. Selected with CE = O E = L, WE = H. Data is valid in tACC time after addresses are stable, tCE after C E is low Read mode and tOE after O E is low. Selected with C E = H. Part is powered down, and ICC reduced to <1.0 A when C E = VCC 0.3V = RE S E T. If activated during an automated on-chip algorithm, the device completes the operation before entering Standby standby. Output disable Part remains powered up; but outputs disabled with O E pulled high. Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command register. Contents of command register serve as inputs to the internal state machine. Address latching occurs Write on the falling edge of WE or CE, whichever occurs later. Data latching occurs on the rising edge WE or CE, whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands. Hardware protection circuitry implemented with external programming equipment causes the device to Enable disable program and erase operations for specified sectors. For in-system sector protection, refer to Sector sector protect protect algorithm on page 12. Disables sector protection for all sectors using external programming equipment. All sectors must be Sector protected prior to sector unprotection. For in-system sector unprotection, refer to Sector unprotect unprotect algorithm on page 12. Verifies write protection for sector. Sectors are protected from program/erase operations on commercial Verify sector programming equipment. Determine if sector protection exists in a system by writing the ID read command protect/ sequence and reading location XXX02h, where address bits A12-17 select the defined sector addresses. A unprotect logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector. Temporarily disables sector protection for in-system data changes to protected sectors. Apply +10V to R ES E T Temporary to activate temporary sector unprotect mode. During temporary sector unprotect mode, program protected sector sectors by selecting the appropriate sector address. All protected sectors revert to protected state on removal unprotect of +10V from R ES E T. Resets the interal state machine to read mode. If device is programming or erasing when RESET = L, data RE SE T may be corrupted. Deep Hold RESET low to enter deep power down mode (<1 A). Recovery time to start of first read cycle is 50ns. power down Enabled automatically when addresses remain stable for 300ns. Typical current draw is 1 A. Existing data is Automatic available to the system during this mode. If an address is changed, automatic sleep mode is disabled and new sleep mode data is returned within standard access times. Item 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 5 of 26 $6/9 )OH[LEOH VHFWRU DUFKLWHFWXUH Sector 0 1 2 3 4 5 6 7 8 9 10 Bottom boot sector architecture (AS29LV400B) x8 x16 Size (Kbytes) 00000h-03FFFh 00000h-01FFFh 16 04000h-05FFFh 02000h-02FFFh 8 06000h-07FFFh 03000h-03FFFh 8 08000h-0FFFFh 04000h-07FFFh 32 10000h-1FFFFh 08000h-0FFFFh 64 20000h-2FFFFh 10000h-17FFFh 64 30000h-3FFFFh 18000h-1FFFFh 64 40000h-4FFFFh 20000h-27FFFh 64 50000h-5FFFFh 28000h-2FFFFh 64 60000h-6FFFFh 30000h-37FFFh 64 70000h-7FFFFh 38000h-3FFFFh 64 Top boot sector architecture (AS29LV400T) x8 x16 Size (Kbytes) 00000h-0FFFFh 00000h-07FFFh 64 10000h-1FFFFh 08000h-0FFFFh 64 20000h-2FFFFh 10000h-17FFFh 64 30000h-3FFFFh 18000h-1FFFFh 64 40000h-4FFFFh 20000h-27FFFh 64 50000h-5FFFFh 28000h-2FFFFh 64 60000h-6FFFFh 30000h-37FFFh 64 70000h-77FFFh 38000h-3BFFFh 32 78000h-79FFFh 3C000h-3CFFFh 8 7A000h-7BFFFh 3D000h-3DFFFh 8 7C000h-7FFFFh 3E000h-3FFFFh 16 In word mode, there are one 8K word, two 4K word, one 16K word, and seven 32K word sectors. Address range is A17-A-1 if B YT E = VIL; address range is A17-A0 if B YT E = VIH. ,' 6HFWRU DGGUHVV WDEOH Sector 0 1 2 3 4 5 6 7 8 9 10 A17 0 0 0 0 0 0 0 1 1 1 1 Bottom boot sector address (AS29LV400B) A16 A15 A14 A13 A12 0 0 0 0 X 0 0 0 1 0 0 0 0 1 1 0 0 1 X X 0 1 X X X 1 0 X X X 1 1 X X X 0 0 X X X 0 1 X X X 1 0 X X X 1 1 X X X A17 0 0 0 0 1 1 1 1 1 1 1 Top boot sector address (AS29LV400T) A16 A15 A14 A13 A12 0 0 X X X 0 1 X X X 1 0 X X X 1 1 X X X 0 0 X X X 0 1 X X X 1 0 X X X 1 1 0 X X 1 1 1 0 0 1 1 1 0 1 1 1 1 1 X 5($' FRGHV Mode MFR code (Alliance Semiconductor) x8 T boot x8 B boot x16 T boot x16 B boot A17-A12 X X X X X Sector address A6 L L L L L L A1 L L L L L H A0 L H H H H L Code 52h B9h BAh 22B9h 22BAh 01h protected 00h unprotected Device code Sector protection Key: L =Low ( 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 6 of 26 $6/9 &RPPDQG IRUPDW Command sequence Reset/Read Reset/ Read x16 x8 x16 x8 x16 Autosele x8 ct ID Read x16 Required 1st bus cycle 2nd bus cycle bus write cycles Address Data Address Data 1 3 XXXh 555h AAAh 555h AAh AAAh 555h 3 AAAh 555h AAh AAh 555h 2AAh 555h 2AAh 55h 555h 2AAh 555h 2AA 555 Program address XXX 2AAh 555h 2AAh 555h 55h F0h AAh Read Address 2AAh 555h 2AAh 55h Read Data 55h 3rd bus cycle Address Data 4th bus cycle Address Data 5th bus cycle 6th bus cycle Address Data Address Data 555h AAAh 555h F0h Read Address 01h Device code 02h Device code 00h MFR code XXX02h Sector protection XXX04h Sector protection Program Address Read Data 22B9h (T) 22BAh (B) B9h(T) BAh(B) 0052h 52h 0001h = protected 0000h = unprotected 0001h=protected 0000h=unprotected Program Data 90h AAAh 555h AAAh 555h 90h AAAh 555h AAAh 555 AAA 90h x8 x16 x8 x16 x8 AAAh 555h AAAh 555 AAA XXX XXX 555h AAAh 555h AAAh XXXh XXXh Program Unlock bypass 4 3 2 2 6 6 1 1 AAh AAh A0h 90h AAh AAh B0h 30h 55h 55h Program data 00h 55h 55h A0h 20h Unlock bypass program Unlock bypass reset Chip Erase Sector Erase x16 x8 x16 x8 555h AAAh 555h AAAh 80h 80h 555h AAAh 555h AAAh AAh AAh 2AAh 555h 2AAh 555h 55h 55h 555h AAAh Sector Address 10h 30h Sector Erase Suspend Sector Erase Resume 1 2 3 4 5 6 Bus operations defined in "Mode definitions," on page 3. Reading from and programming to non-erasing sectors allowed in Erase Suspend mode. Address bits A11-A17 = X = Don't Care for all address commands except where Program Address and Sector Address are required. Data bits DQ15-DQ8 are don't care for unlock and command cycles. The Unlock Bypass command must be initiated before the Unlock Bypass Program command. The Unlock Bypass Reset command returns the device to reading array data when it is in the unlock bypass mode. 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 7 of 26 $6/9 &RPPDQG GHILQLWLRQV Item Description Initiate read or reset operations by writing the Read/Reset command sequence into the command register. This allows the microprocessor to retrieve data from the memory. Device remains in read mode until command register contents are altered. Device automatically powers up in read/reset state. This feature allows only reads, therefore ensuring no spurious memory content alterations during power up. AS29LV400 provides manufacturer and device codes in two ways. External PROM programmers typically access the device codes by driving +10V on A9. AS29LV400 also contains an ID Read command to read the device code with only +3V, since multiplexing +10V on address lines is generally undesirable. ID Read Initiate device ID read by writing the ID Read command sequence into the command register. Follow with a read sequence from address XXX00h to return MFR code. Follow ID Read command sequence with a read sequence from address XXX01h to return device code. To verify write protect status on sectors, read address XXX02h. Sector addresses A17-A12 produce a 1 on DQ0 for protected sector and a 0 for unprotected sector. Exit from ID read mode with Read/Reset command sequence. Holding RE S E T low for 500 ns resets the device, terminating any operation in progress; data handled in the operation is corrupted. The internal state machine resets 20 s after RE S E T is driven low. RY/BY remains low until internal state machine resets. After R E S ET is set high, there is a delay of 50 ns for the device to permit read operations. Programming the AS29LV400 is a four bus cycle operation performed on a byte-by-byte or wordby-word basis. Two unlock write cycles precede the Program Setup command and program data write cycle. Upon execution of the program command, no additional CPU controls or timings are necessary. Addresses are latched on the falling edge of C E or WE , whichever is last; data is latched on the rising edge of CE or WE , whichever is first. The AS29LV400's automated on-chip program algorithm provides adequate internally-generated programming pulses and verifies the programmed cell margin. Check programming status by sampling data on the RY/BY pin, or either the DATA polling (DQ7) or toggle bit (DQ6) at the program address location. The programming operation is complete if DQ7 returns equivalent data, if DQ6 = no toggle, or if RY/BY pin = high. The AS29LV400 ignores commands written during programming. A hardware reset occurring during programming may corrupt the data at the programmed location. AS29LV400 allows programming in any sequence, across any sector boundary. Changing data from 0 to 1 requires an erase operation. Attempting to program data 0 to 1 results in either DQ5 = 1 (exceeded programming time limits); reading this data after a read/reset operation returns a 0. When programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this state, a Reset command returns the device to read mode. Reset/Read Hardware Reset Byte/word Programming 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 8 of 26 $6/9 Item Description The unlock bypass feature increases the speed at which the system programs bytes or words to the device because it bypasses the first two unlock cycles of the standard program command sequence. To initiate the unlock bypass command sequence, two unlock cycles must be written, then followed by a third cycle which has the unlock bypass command, 20h. Unlock Bypass Command Sequence The device then begins the unlock bypass mode. In order to program in this mode, a two cycle unlock bypass program sequence is required. The first cycle has the unlock bypass program command, A0h. It is followed by a second cycle which has the program address and data. To program additional data, the same sequence must be followed. The unlock bypass mode has two valid commands, the Unlock Bypass Program command and the Unlock Bypass Reset command. The only way the system can exit the unlock bypass mode is by issuing the unlock bypass reset command sequence. This sequence involves two cycles. The first cycle contains the data, 90h. The second cycle contains the data 00h. Addresses are don't care for both cycles. The device then returns to reading array data. Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional unlock write cycles; and finally the Chip Erase command. Chip Erase Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip erase algorithm is invoked with the Chip Erase command sequence, AS29LV400 automatically programs and verifies the entire memory array for an all-zero pattern prior to erase. The 29LV400 returns to read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding time limit. Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional unlock write cycles, and finally the Sector Erase command. Identify the sector to be erased by addressing any location in the sector. The address is latched on the falling edge of WE ; the command, 30h is latched on the rising edge of WE . The sector erase operation begins after a sector erase time-out. To erase multiple sectors, write the Sector Erase command to each of the addresses of sectors to erase after following the six bus cycle operation above. Timing between writes of additional sectors must be less than the erase time-out period, or the AS29LV400 ignores the command and erasure begins. During the time-out period any falling edge of WE resets the time-out. Any command (other than Sector Erase or Erase Suspend) during time-out period resets the AS29LV400 to read mode, and the device ignores the sector erase command string. Erase such ignored sectors by restarting the Sector Erase command on the ignored sectors. The entire array need not be written with 0s prior to erasure. AS29LV400 writes 0s to the entire sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected sectors unaffected. AS29LV400 requires no CPU control or timing signals during sector erase operations. Automatic sector erase begins after sector erase time-out from the last rising edge of WE from the sector erase command stream and ends when the DATA polling (DQ7) is logical 1. DATA polling address must be performed on addresses that fall within the sectors being erased. AS29LV400 returns to read mode after sector erase unless DQ5 is set high by exceeding the time limit. Sector Erase 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 9 of 26 $6/9 Item Description Erase Suspend allows interruption of sector erase operations to read data from or program data to a sector not being erased. Erase suspend applies only during sector erase operations, including the time-out period. Writing an Erase Suspend command during sector erase time-out results in immediate termination of the time-out period and suspension of erase operation. AS29LV400 ignores any commands during erase suspend other than Read/Reset, Program or Erase Resume commands. Writing the Erase Resume Command continues erase operations. Addresses are Don't Care when writing Erase Suspend or Erase Resume commands. AS29LV400 takes 0.2-15 s to suspend erase operations after receiving Erase Suspend command. To determine completion of erase suspend, either check DQ6 after selecting an address of a sector not being erased, or poll RY/BY. Check DQ2 in conjunction with DQ6 to determine if a sector is being erased. AS29LV400 ignores redundant writes of Erase Suspend. While in erase-suspend mode, AS29LV400 allows reading data (erase-suspend-read mode) from or programming data (erase-suspend-program mode) to any sector not undergoing sector erase; these operations are treated as standard read or standard programming mode. AS29LV400 defaults to erase-suspend-read mode while an erase operation has been suspended. Write the Resume command 30h to continue operation of sector erase. AS29LV400 ignores redundant writes of the Resume command. AS29LV400 permits multiple suspend/resume operations during sector erase. When attempting to write to a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for about <1 s. When attempting to erase a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for about <5 s. In both cases, the device returns to read mode without altering the specified sectors. RY/BY indicates whether an automated on-chip algorithm is in progress (RY/BY = low) or completed (RY/BY = high). The device does not accept Program/Erase commands when RY/BY = low. RY/BY= high when device is in erase suspend mode. RY/BY = high when device exceeds time limit, indicating that a program or erase operation has failed. RY/BY is an open drain output, enabling multiple RY/BY pins to be tied in parallel with a pull up resistor to VCC. Erase Suspend Sector Protect Ready/Busy 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 10 of 26 $6/9 6HFWRU SURWHFW DOJRULWKP START PLSCNT = 1 RESET# = VID Wait 1 s 6HFWRU XQSURWHFW DOJRULWKP START PLSCNT = 1 RESET# = VID Wait 1 s Temporary sector unprotect mode No First Write Cycle=60h? Yes Set up sector address Sector protect: write 60h to sector address with A6=0, A1=1, A0=0 Wait 150 s Verify sector protect; write 40h to sector address with A6=0, A1=1, A0=0 Read from sector address with A6=0, A1=1, A0=0 Protect all sectors: The shaded portion of the sector protct algorithm must be initiated for all unprotected sectors before calling the sector unprotect First Write Cycle=60h? Yes No All sectors protected? Yes Sector unprotect: write 60h to sector address with A6=1, A1=1, A0=0 Wait 15 ms Set up first sector address Verify sector unprotect; write 40h to sector address with A6=1, A1=1, A0=0 Read from sector address with A6=1, A1=1, A0=0 No Temporary sector unprotect mode Increment PLSCNT No No Increment PLSCNT PLSCNT=25? Data=01h? No Yes Yes Protect another sector? No Remove VID from RESET# Write reset command Sector protect complete Yes PLSCNT =1000? No Data=00h? Yes Yes Last sector verified? Yes Remove VID from RESET# Write reset command Sector unprotect complete No Set up next sector address Device failed Device failed 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 11 of 26 $6/9 6WDWXV RSHUDWLRQV DATA polling (DQ7) Toggle bit 1 (DQ6) Exceeding time limit (DQ5) Sector erase timer (DQ3) Toggle bit 2 (DQ2) Only active during automated on-chip algorithms or sector erase time outs. DQ7 reflects complement of data last written when read during the automated on-chip program algorithm (0 during erase algorithm); reflects true data when read after completion of an automated on-chip program algorithm (1 after completion of erase agorithm). Active during automated on-chip algorithms or sector erase time outs. DQ6 toggles when C E or O E toggles, or an Erase Resume command is invoked. DQ6 is valid after the rising edge of the fourth pulse of WE during programming; after the rising edge of the sixth WE pulse during chip erase; after the last rising edge of the sector erase WE pulse for sector erase. For protected sectors, DQ6 toggles for <1 s during program mode writes, and <5 s during erase (if all selected sectors are protected). Indicates unsuccessful completion of program/erase operation (DQ5 = 1). DATA polling remains active. If DQ5 = 1 during chip erase, all or some sectors are defective; during byte programming or sector erase, the sector is defective (in this case, reset the device and execute a program or erase command sequence to continue working with functional sectors). Attempting to program 0 to 1 will set DQ5 = 1. Checks whether sector erase timer window is open. If DQ3 = 1, erase is in progress; no commands will be accepted. If DQ3 = 0, the device will accept sector erase commands. Check DQ3 before and after each Sector Erase command to verify that the command was accepted. During sector erase, DQ2 toggles with O E or C E only during an attempt to read a sector being erased. During chip erase, DQ2 toggles with O E or CE for all addresses. If DQ5 = 1, DQ2 toggles only at sector addresses where failure occurred, and will not toggle at other sector addresses. Use DQ2 in conjunction with DQ6 to determine whether device is in auto erase or erase suspend mode. :ULWH RSHUDWLRQ VWDWXV Standard mode Status Auto programming Program/erase in auto erase Read erasing sector Read non-erasing sector Program in erase suspend Auto programming (byte) Program/erase in auto erase Program in erase suspend (non-erase suspended sector) DQ7 DQ7 0 1 Data DQ7 DQ7 0 DQ7 DQ6 Toggle Toggle No toggle Data Toggle Toggle Toggle Toggle DQ5 0 0 0 Data 0 1 1 1 DQ3 N/A 1 N/A Data N/A N/A N/A N/A DQ2 No toggle Toggle Toggle Data Toggle No toggle Toggle No toggle RY/BY 0 0 1 1 0 1 1 1 Erase suspend mode Exceeded time limits DQ2 toggles when an erase-suspended sector is read repeatedly. DQ6 toggles when any address is read repeatedly. DQ2 = 1 if byte address being programmed is read during erase-suspend program mode. DQ2 toggles when the read address applied points to a sector which is undergoing erase, suspended erase, or a failure to erase. 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 12 of 26 $6/9 $XWRPDWHG RQFKLS SURJUDPPLQJ DOJRULWKP START $XWRPDWHG RQFKLS HUDVH DOJRULWKP START Write erase command sequence (see below) Write program command sequence (see below) DATA polling or toggle bit successfully completed DATA polling or toggle bit successfully completed Erase complete Increment address Chip erase command sequence x16 mode (address/data): 555h/AAh Individual sector/multiple sector erase command sequence x16 mode (address/data): 555h/AAh Last address? NO YES Programming completed 2AAh/55h 2AAh/55h 555h/80h 555h/80h Program command sequence x16 mode (address/data): 555h/AAh 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 2AAh/55h 555h/10h Sector address/30h 555h/A0h Sector address/30h Program address/program data Sector address/30h optional sector erase commands The system software should check the status of DQ3 prior to and following each subsequent sector erase command to ensure command completion. The device may not have accepted the command if DQ3 is high on second status check. 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 13 of 26 $6/9 3URJUDPPLQJ XVLQJ XQORFN E\SDVV FRPPDQG Unlock bypass command sequence START x16 mode (address/data) 555h/AAh Write unlock bypass command (3 cycles) 2AAh/55h 555h/20h Write unlock bypass program command (2 cycles) Unlock bypass program command sequence x16 mode (address/data) DATA polling or toggle bit successfully completed Increment address Last address? NO xxxh/A0h program address/ program data Unlock bypass reset command sequence x16 mode (address/data) YES xxxh/90h Write unlock bypass reset command (2 cycles) xxxh/00h Programming completed 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 14 of 26 $6/9 'DWD SROOLQJ DOJRULWKP Read byte (DQ0-DQ7) Address = VA 7RJJOH ELW DOJRULWKP Read byte (DQ0-DQ7) Address = don't care DQ7 = data ? NO NO DQ5 = 1 ? YES YES DONE DQ6 = toggle ? YES NO DQ5 NO DONE = 1 ? YES Read byte (DQ0-DQ7) Address = don't care Read byte (DQ0-DQ7) Address = VA DQ7 = data ? NO FAIL YES DONE DQ6 = toggle ? YES FAIL NO DONE VA = Byte address for programming. VA = any of the sector addresses within the sector being erased during Sector Erase. VA = valid address equals any non-protected sector group address during Chip Erase. DQ7 rechecked even if DQ5 = 1 because DQ5 and DQ7 may not change simultaneously. DQ6 rechecked even if DQ5 = 1 because DQ6 may stop toggling when DQ5 changes to 1. 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 15 of 26 $6/9 '& HOHFWULFDO FKDUDFWHULVWLFV Parameter Input load current A9 Input load current Output leakage current Active current, read @ 5MHz Active current, program/erase Automatic sleep mode* Standby current Deep power down current3 Input low voltage Input high voltage Output low voltage Output high voltage Low VCC lock out voltage Input HV select voltage Symbol Test conditions ILI ILIT ILO ICC1 ICC2 ICC3 ISB IPD VIL VIH VOL VOH VLKO VID IOL = 4.0mA, VCC = VCC MIN IOH = -2.0 mA, VCC = VCC MIN VIN = VSS to VCC, VCC = VCC MAX VCC = VCC MAX, A9 = 10V VOUT = VSS to VCC, VCC = VCC MAX C E = VIL, O E = VIH C E = VIL, O E = VIH C E = VIL, O E = VIH; 9&& Min Max 1 35 -0.5 0.7xVCC 0.85xVCC 1.5 9 1 20 100 5 5 5 0.8 9 Unit A A A mA mA A A A V V V V V V VIL= 0.3V, VIH = VCC - 0.3V C E = VCC - 0.3V, R E S ET = VCC - .3V R E S E T = 0.3V VCC + 0.3 0.45 11 * Automatic sleep mode enables the deep power down mode when addresses are stable for 150 ns. Typical sleep mode current is 200 nA. 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 16 of 26 $6/9 $& SDUDPHWHUV UHDG F\FOH JEDEC Symbol tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Std Symbol tRC tACC tCE tOE tOES tDF tDF tOH tOEH tPHQV tRH tREADY tRP Parameter Read cycle time Address to output delay Chip enable to output Output enable to output Output enable setup time Chip enable to output High Z Output enable to output High Z Output hold time from addresses, first occurrence of CE or OE Output enable hold time: Read Output enable hold time: Toggle and data polling R E SE T high to output delay R E SE T pin low to read mode R E SE T pulse -70 Min Max 70 70 70 30 0 20 20 0 10 10 500 50 10 -80 -90 -120 Min Max Min Max Min Max 80 90 120 80 90 120 80 90 120 30 35 50 0 0 0 20 30 30 20 30 30 0 10 10 500 50 10 0 10 10 500 50 10 0 10 10 500 50 10 Unit ns ns ns ns ns ns ns ns ns ns ns s ns 5HDG ZDYHIRUP tRC Addresses Addresses stable tACC CE tDF tOE OE tOEH WE tCE Outputs High Z tRH tOH Output valid High Z tOES R ES E T 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 17 of 26 $6/9 $& SDUDPHWHUV ZULWH F\FOH JEDEC Symbol tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tELWL tWHEH tWLWH tWHWL -70 Std Symbol Parameter tWC tAS tAH tDS tDH tGHWL tCS tCH tWP tWPH Write cycle time Address setup time Address hold time Data setup time Data hold time Read recover time before write C E setup time C E hold time Write pulse width Write pulse width high Min 70 0 45 35 0 0 0 0 35 30 Max Min 80 0 45 35 0 0 0 0 35 30 -80 Max Min 90 0 45 45 0 0 0 0 35 30 -90 Max - WE FRQWUROOHG -120 Min Max Unit 120 0 50 50 0 0 0 0 50 30 ns ns ns ns ns ns ns ns ns ns :ULWH ZDYHIRUP WWC Addresses 555h 3rd bus cycle WE FRQWUROOHG WAS WAH DATA polling Program address Program address WCH CE WGHWL; tOES OE WWP WE WWHWH1 or 2 WCS A0h WWPH WDH WDS Program data DATA D Q DOUT 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 18 of 26 $6/9 $& SDUDPHWHUV ZULWH F\FOH JEDEC Symbol tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL -70 Std Symbol tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH Parameter Write cycle time Address setup time Address hold time Data setup time Data hold time Read recover time before write WE setup time WE hold time C E pulse width C E pulse width high Min 70 0 45 35 0 0 0 0 35 30 Max Min 80 0 45 35 0 0 0 0 35 30 -80 Max Min 90 0 45 45 0 0 0 0 35 30 -90 Max - C E FRQWUROOHG -120 Min Max Unit 120 0 50 50 0 0 0 0 50 30 ns ns ns ns ns ns ns ns ns ns :ULWH ZDYHIRUP DATA polling Addresses 555h tWC Program address tAS tAH Program address C E FRQWUROOHG WE tGHEL, tOES OE tCP tWHWH1 or 2 tCPH tDH CE DATA A0h tDS Program data DQ 7 DOUT 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 19 of 26 $6/9 $& SDUDPHWHUV WHPSRUDU\ VHFWRU XQSURWHFW JEDEC Symbol Std Symbol tVIDR tRSP -70 Parameter VID rise and fall time RE S E T setup time for temporary sector unprotect Min 500 4 Max Min 500 4 -80 Max Min 500 4 -90 Max -120 Min Max 500 4 Unit ns s 7HPSRUDU\ VHFWRU XQSURWHFW ZDYHIRUP R E S ET CE WE tRSP 10V 0 or 3V tVIDR Program/erase command sequence tVIDR 0 or 3V RY/B Y $& SDUDPHWHUV R E SE T JEDEC Symbol Std Symbol tRP tRH tREADY -70 Parameter RE S E T pulse RE S E T High time before Read RE S E T Low to Read mode Min 500 Max 50 10 Min 500 -80 Max 50 10 Min 500 -90 Max 50 10 Min 500 -120 Max 50 10 Unit ns ns s R ES E T ZDYHIRUP RESET RY/BY DQ status tRP tREADY tRH status valid data valid data tRP (UDVH ZDYHIRUP tWC Addresses 555h i PRGH tAS 2AAh 555h 555h 2AAh Sector address tAH CE tGHWL OE tWP tWC tWPH tDH AAh 55h 80h AAh 55h 10h for Chip Erase 30h WE tCS Data tDS 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 20 of 26 $6/9 $& 3DUDPHWHUV 5($'<%86< JEDEC Symbol Std Symbol tVCS tRB tBUSY Parameter VCC setup time Min 50 0 90 -70 Max -80 Min Max 50 0 90 -90 Min Max 50 0 90 -120 Min Max 50 0 90 Unit s ns ns Recovery time from RY/BY Program/erase valid to RY/BY delay RY/BY ZDYHIRUP CE WE RY/B Y VCC Rising edge of last WE signal tri-stated open-drain tBUSY Program/erase operation tRB tVCS '$7$ SROOLQJ ZDYHIRUP CE tCH tOE OE tOEH WE tCE tOH DQ7 Input DQ7 Output DQ Output High Z tDF tWHWH1 or 2 7RJJOH ELW ZDYHIRUP CE tOEH WE OE DQ6 tDH tOE toggle toggle no toggle 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 21 of 26 $6/9 :RUGE\WH FRQILJXUDWLRQ JEDEC Symbol Std Symbol tELFL/tELFH tFLQZ tFHQZ Parameter C E to BYTE switching Low or High B YT E switching Low to output High-Z B YT E switching High to output Active Min 70 -70 Max 10 30 -80 Min Max 80 10 30 -90 Min Max 90 10 35 -120 Min Max 120 10 40 Unit ns ns ns %<7( UHDG ZDYHIRUP CE OE B YTE Word to Byte tELFL DQ0-DQ14 DQ15/A-1 B YTE tELFH DQ0-DQ14 Data output DQ15 output tFLQZ DQ0-DQ7 Data output Address input Byte to Word DQ0-DQ14 DQ15/A-1 DQ0-DQ7 Data output Address input tFHQV DQ0-DQ14 Data output DQ15 output B YTE ZULWH ZDYHIRUP CE falling edge of last WE signal WE BY TE See Erase/Program operations table for tAS and tAH specifications. tSET (tAS) tHOLD (tAH) 6HFWRU SURWHFWXQSURWHFW R E S ET # VID VIH SA, A6, A1, A0 DATA 1 s Don't care Valid* Don't care Valid* Verify 40h Don't care Valid* Sector protect/unprotect 60h 60h Don't care Sector protect: 100 s Sector unprotect: 10 ms Don't care Status CE# WE# OE# * For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0. 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 22 of 26 $6/9 $& WHVW FRQGLWLRQV 1 RU HTXLYDOHQW 'HYLFH XQGHU WHVW &/ . 9 . 1 RU HTXLYDOHQW 966 966 966 7HVW VSHFLILFDWLRQV -70, Test Condition Output Load Output Load Capacitance CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels -90, -120 1 TTL gate 100 5 0.0-3.0 1.5 1.5 -80 30 Unit pF ns V V V (UDVH DQG SURJUDPPLQJ SHUIRUPDQFH Parameter Sector erase and verify-1 time (excludes 00h programming prior to erase) Programming time Chip programming time Erase/program cycles* * Erase/program cycle test is not verified on each shipped unit. Min Limits Typical 1.0 10 15 7.2 100,000 Max 15 300 360 27 - Unit sec s s sec cycles Byte Word - /DWFKXS WROHUDQFH Parameter Input voltage with respect to VSS on A9, OE and RESET pin Input voltage with respect to VSS on all DQ, address, and control pins Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. Min -1.0 -0.5 -100 Max +12.0 Unit V V mA VCC+0.5 +100 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 23 of 26 $6/9 5HFRPPHQGHG RSHUDWLQJ FRQGLWLRQV Parameter Supply voltage Input voltage Symbol VCC VSS VIH VIL Min +2.7 0 1.9 -0.5 Max +3.6 0 VCC + 0.3 0.8 Unit V V V V $EVROXWH PD[LPXP UDWLQJV Parameter Input voltage (Input or DQ pin) Input voltage (A9 pin, OE , RES ET ) Power supply voltage Operating temperature Storage temperature (plastic) Short circuit output current Symbol VIN VIN VCC TOPR TSTG IOUT Min -0.5 -0.5 -0.5 -55 -65 Max VCC+ 0.5 +12.5 +4.0 +125 +150 150 Unit V V V C C mA Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 7623 SLQ FDSDFLWDQFH Symbol CIN COUT CIN2 Parameter Input capacitance Output capacitance Control pin capacitance Test setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 8 Max 7.5 12 10 Unit pF pF pF 62 SLQ FDSDFLWDQFH DYDLODEOLW\ 7%' Symbol CIN COUT CIN2 Parameter Input capacitance Output capacitance Control pin capacitance Test setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 8 Max 7.5 12 10 Unit pF pF pF 'DWD UHWHQWLRQ Parameter Minimum pattern data retention time Temp.(C) 150 125 Min 10 20 Unit years years 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 24 of 26 $6/9 7KLQ 6PDOO 2XWOLQH 3DFNDJH 7623 Package dimensions c L pin 1 A2 pin 48 A A1 b e 48-pin 12x20 A A1 A2 b c D e E Hd L Min Max - 1.20 0.05 0.15 0.95 1.05 0.17 0.27 0.15 nominal 18.20 18.60 0.50 nominal 11.90 12.10 19.80 20.20 0.50 0.70 0 5 D Hd pin 24 48-pin pin 25 E 6PDOO 2XWOLQH SODVWLF SDFNDJH 62 Package dimensions JEDEC MO - 175 AA 44-pin SO Min Max (mm) (mm) A - 3.1 A1 0.05 - A2 2.5 2.9 b 0.25 0.45 c 0.09 0.25 d 28.0 28.4 e 12.4 12.8 E 1.27 (typical) He 16.05 (typical) l 0.73 1.3 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 c SO e He 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0-10 d A2 A1 b E A l 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 25 of 26 $6/9 $6/9 RUGHULQJ FRGHV Package \ Access Time TSOP, 12x20 mm, 48-pin Top boot configuration TSOP, 12x20 mm, 48-pin Bottom boot configuration SO*, 13.3 mm, 44-pin Top boot configuration SO, 13.3 mm, 44-pin Bottom boot configuration 70ns(commercial and industrial) AS29LV400T-70TC AS29LV400T-70TI AS29LV400B-70TC AS29LV400B-70TI AS29LV400T-70SC AS29LV400T-70SI AS29LV400B-70SC AS29LV400B-70SI 80ns(commercil and industrial) AS29LV400T-80TC AS29LV400T-80TI AS29LV400B-80TC AS29LV400B-80TI AS29LV400T-80SC AS29LV400T-80SI AS29LV400B-80SC AS29LV400B-80SI 90ns(commercial and industrial) AS29LV400T-90TC AS29LV400T-90TI AS29LV400B-90TC AS29LV400B-90TI AS29LV400T-90SC AS29LV400T-90SI AS29LV400B-90SC AS29LV400B-90SI 120ns(commercial and industrial) AS29LV400T-120TC AS29LV400T-120TI AS29LV400B-120TC AS29LV400B-120TI AS29LV400T-120SC AS29LV400T-120SI AS29LV400B-120SC AS29LV400B-120SI VKDGHG DUHD LQGLFDWHV DGYDQFHG LQIRUPDWLRQ DYDLODELOLW\ RI 62 SDFNDJH LV 7%' $6/9 SDUW QXPEHULQJ V\VWHP AS29LV 3V Flash EEPROM prefix 400 X -XXX Address access time X Package: S = SO* T = TSOP X Temperature range: C = Commercial: 0C to 70C I = Industrial: -40C to 85C Device T= Top boot configuration number B= Bottom boot configuration X Options: B = Burn-in H = High ISB (<1mA) Blank= Standard 9/26/01; V.0.9.9.2 $OOLDQFH 6HPLFRQGXFWRU P. 26 of 26 (c) Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. |
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